Typically, a printed circuit board (hereinafter referred to as PCB) is comprised of at least one layer of dielectric substrate, usually fabricated from epoxy coated glass fabric and one or two sides of thin layer of predetermined pattern of metallic traces, such as copper. Interconnections between the layers of metallic circuitry are often required to enforce electrical communication between the various metallic layers. Pursuant to the existing prior art printed circuit boards are produced by laminating layers of copper foils to a dielectric substrate to form a copper clad laminate. That copper clad laminate is further processed to convert the copper foils into predetermined circuit patterns by selectively removing portions of the copper foils through the use of chemical etching techniques. PCBs produced by conventional, prior art processes are characterized by outerlayer circuits bonded on top of the dielectric substrate as shown in FIG. 1. However, conventional approaches have several shortcomings. As an example etchants must remove large amount of copper, which increases both manufacturing costs and waste disposal costs. A further disadvantage regarding conventional methods is that existing etchants do not create vertical sides of the circuit lines. Instead, these etchants tend to etch away too much copper at the top and too little copper at the bottom of the circuit lines, creating a trapezoidal-shaped circuit lines, and resulting in a phenomenon described in the industry as the etching factor effect. As a result, the minimum width of the circuit lines and the minimum spaces between circuit lines are limited due to uneven and inaccurate etching. An approach to improving the accuracy of the circuit lines is to use thinner copper foil, which are capable of being quickly etched with less undercutting. However, such thin copper foils are not only expensive but also difficult to handle. For much thinner copper foil a carrier layers is usually applied to improve operability, one such example is found in U.S. Pat. No. 3,998,601 in which a thin copper foil is deposited on a supportive thick copper foil and then separated from the thick copper foil by a release layer.
Another known alternative method for forming fine-line patterns is shown in U.S. Pat. No. 6,117,300 to Carbin et al. According to the technique of Carbin et al., a thin conductive layer is applied to a substrate using a foil carrier; a photoresist may then be applied, imaged, and cured. The uncured photoresist may be removed, thereby defining some exposed regions or on the surface of the substrate in which the circuit lines are to be formed. Since the conductive layer is now exposed, it is possible to selectively apply the circuit lines in those exposed regions. Finally, the cured photoresist is removed and the exposed conductive metal layer beneath the photoresist is removed, leaving the finished circuit pattern. An earlier technique for fabricating printed circuit boards by pattern plating process is described in the U.S. Pat. No. 5,733,468 issued to Conway. In accordance with the latter technique Conway teaches, a thin, first layer of copper foil being bonded to the surface of the board, then a photoresist layer is laminated over the copper layer, and wherein the photoresist is selectively exposed and developed to define the desired pattern of traces. A thick, second layer of copper is electrodeposited on the traces and the photoresist is then removed. The board is etched to remove those portions of the first copper layer that are not covered by the second copper layer, and thus leaving the finished circuit pattern.
As circuit lines become finer, an obvious disadvantage, of the aforementioned techniques is that the copper traces may not adhere sufficiently to the dielectric layer, which may be peeled off from the dielectric layer during surface conditioning, such as brushing prior to soldermask printing. An improved technique also known as “imprint patterning” is described in U.S. Pat. No. 6,005,198 issued to Gregoire. Pursuant to the teachings of Gregoire, a U-shape recessed pattern of circuitry is formed on the surface of a compressible substrate via a stamping process, then a conducter is disposed on the surface of the recessed pattern by electroplating or metal transfer. While Gregoire technique has advantages in forming circuit lines and micro-vias integrally, the need for new substrate material, and the reduction in fidelity and reliability of the delicate mold after repetitive stamping are examples of disadvantages. Other disadvantage associated with fine line printed circuit board are its irregular and zigzag surface formed by the dense circuit lines, the difficulties associated with filling soldermask and air entrapment along the narrow spaces of the finer circuit pattern, which result in bubbling, blistering or delaminating of soldermask upon passing the solder bath. A further disadvantage of the conventional techniques in forming very thin multilayer PCB is that the copper clad laminate tends to shrink and warp after exposure to chemicals and/or high temperature, resulting in mismatch of circuit lines of different layers. All these shortcomings result in numerous quality control problems and require costly capital equipment and manufacturing tolerance.
Bearing the aforementioned shortcomings in mind, consequently, there exists a need for PCB with inlaid outer-layer circuits which use economical and reliable production methods and capable of overcoming the above-identified shortcomings.